Reducing the PCB in size certainly has some benefits , however, the reduction of surface area can also easily reduce thermal performance, if care is not taken. The LED driver chip LT3496 has a rather large (compared to the size of the chip 😉 ) thermal pad on the underside that is reflow soldered onto the top ground plane of the PCB. Also thermal vias are placed directly under the pad and surrounding area to help conduct the heat to the bottom ground plane. Both planes serve as heat spreaders. So the question that interested me was how much ground plane is necessary and how many vias are needed, what size should they have and how densely (or not) should they be spaced ?
Fortunately in these times there is abundant information available about such topics on the Internet. I’ve read a good number of forum posts and blog entries and then there are also several application notes from well known Companies that deal with thermal issues in detail. In the past I’ve found that Application Notes in particular provide a lot of valuable and often well researched information directly from the developers, so here is a list of four that I found to be particularly helpful:
This first one is from Texas Instruments and explains contains some directly applicable guidelines. While the paper deals with TI’s PowerPAD™ Chips, the chip size and size of he thermal pad are very similar to the LT3496. It provides recommendations on via size, spacing etc.
The next paper is also from Texas Instruments and delves a little deeper into the theory and provides the mathematical tools if one is inclined to do some calculations. The links to some online calculators help saving paper. Here the thickness of the copper layers is given some thought and recommendations are provided.
The next one is from Infineon, published in January 2000 and provides some more theory and application examples.
The last one I want to share here is from Cree and contains some experimental data. Consideration is given to different cooling surface area, size and spacing of the thermal vias and something that I had not yet crossed my mind , board thickness.
The question is now how does all that accumulated knowledge result in a better shield design. Well, lets see…
- The first thing to do is to maximize the surface area that can dissipate heat and to make sure that there are no breaks in the surface or at least not perpendicular to the flow of heat. Thus I redesigned the lower part of the PCB. The DAC was moved down so the 0-ohm -&-capacitor triplet could be moved to the right to clear some space toward the right side of the chip. The loop to connect the SHDN with VCC was retraced to the right side of the board to clear some space on the left side of the chip. These changes mostly concerned the top ground plane. The design in the last post already provided a more symmetric heat spreader around the chip on the bottom ground plane and I’ve fine-tuned tracing a little to provide less interruptions close to the chip.
- Next I looked into vias. The optimum size recommended in most of the above papers is 12 – 10 mil (0.3 – 0.25mm). Vias larger than that are able to transfer more heat due their larger cross-section, but the danger is that gravity pulls the solder way from the thermal pad and voids can reduce the contact area between the thermal bad the the board. For now the board uses 12 mil vias, as that is a size most low volume board houses are able to manufacture. If we pull the trigger on a manufacturer and they are able to do 10 mil vias we may choose that smaller size for the area immediately under the thermal pad. The more vias the better and the spacing recommendations range from 1mm in two of the above paper to 0.6mm in the Cree paper. In our board the spacing is 0.6mm. The original design already provided these features/details, so there is another kudos to the neuroelec! The more I research, explore and play with LED driver design, the more I am impressed with the excellent job that was done already with the initial design!
Another thing that can be seen in the Cree paper is that any vias that are not normal to, or directly under the thermal pad of the chip provide very little if any benefit, and may even be counterproductive as they also reduce the cross-sectional area of the copper layers that serve as heat spreaders and cooling surface. Along the way I integrated the thermal pad and vias into the Eagle package, so now this is reusable and also eliminates the pesky DRC check errors.
- There are really only two things left should all the above not provide enough cooling. Nothing beats a nice, solid metal heat sink and some airflow. Chances are that if you are runing the board that close o the limit you’ve spend so much on LEDs that a few bucks for a heatsink and a little fan won’t make much a difference anymore. The question is of course where to install that heatsink. It seems only intuitive to mount it on top of the chip, however, the thermal resistance toward the bottom of the PCB is smaller than the path toward the top of the chip. So I left an area of 19 x 7 mm free of solder mask, so a heat sink can be glued to that surface by means of thermal epoxy. This provides enough surface for a “traditional” finned Fischer Elektronik ICK SMD A 17 or ICK SMD B 7. The A17 is available at Newark.com for $0.8.
- As previously mentioned the thickness of the copper also makes a substantial contribution to the thermal performance thus the board uses 2oz (70μm) copper.
There are a couple of other possibilities that would benefit the heat transfer between the chip and the bottom surface that are also described in the papers above that are not yet implemented. One is the thickness of the board, with the standard PCB being 1.6 m thick. A 0.8mm thick board provides a much shortened thermal path from the thermal pad to the underside of the board and can also significantly contribute to better thermal behavior. This may be an option, depending on pricing. Literature also suggests that capped and filled, or copper-plugged vias greatly enhance performance but do not recommend these due to the cost impact.
In essence, even without the latter two options I suggest that the thermal performance is better than the original design, despite the smaller overall size of the board. It would be great to be able verify these improvements with some thermal imaging….
As such, her is the slightly redesigned board once more. Now it’s time to make a few prototypes and a SMD stencil from Pololu is on order. There is no rush, however, as I intend to order ther prototype boards from Iteadstudio. While they don’t have the 2oz copper, the price is hard to beat, at least for prototyping. Alas, the Chinese Newyear festivities should be in full swing and only limited order processing has was announced, so the 5 sets of component that I already have will have to wait a little longer for action.